(1) FIELD OF THE INVENTION
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of fabricating a raised contact to achieve ultra-shallow junction devices in the fabrication of integrated circuits.
(2) DESCRIPTION OF THE PRIOR ART
In the fabrication of integrated circuit devices, as the ground rule shrinks below a sub-250 nm regime, a shallow junction (less than 100 nm) is required. Although substantial progress has been made to form a shallow junction by utilizing low energy implantation followed by a rapid thermal process (RTP) anneal, little attention has been paid to contact formation over the shallow junction. To fabricate fully functional devices, a healthy contact needs to be made to provide low resistance contact to a source/drain junction surface. However, a concurrent achievement of low resistance and shallow contact is not trivial due to a principle limitation: to form low resistance, a high dose implantation is needed and to form a shallow junction, a low energy implantation is needed.
A low energy implantation suffers from a low beam current due to its space charge limitation principle. In order to form a low resistant contact, a high dose implantation is needed to overcome the Schottky barrier to form an ohmic contact. However, due to the space charge limited current criteria, a high energy implantation is needed. Therefore, generally a high dose (higher than that of the junction) and high energy (higher than that of the junction) contact implantation is performed, but located away from a gate side. This will result in a deeper contact junction than the depth of the source/drain junction. As the ground rule shrinks, overlap control does not improve as much as critical dimension control resulting in poor misalignment ( greater than 30%) between layers. This will result in contact to gate electrode misalignment. Thus, the deeper contact junction will impact device performance causing a short-channel effect (SCE) and threshold voltage lowering.
The contact junction is typically implanted onto a bare silicon surface while the source/drain junction is implanted through a screen oxide. For a low energy implantation, a significant portion of the dopants, more than 50%, remain within the screen oxide. To ultimately resolve the contact issue for future devices, a raised contact formation will be ideal.
A number of patents have addressed aspects of junction and contact fabrication. U.S. Pat. No. 6,009,691 to Ang et al discloses a method for forming source/drains without using selective epitaxial growth. U.S. Pat. No. 6,008,104 to Schrems shows a DRAM process with plasma doped source/drains, several selective etches, and a contact process. U.S. Pat. No. 5,904,770 to Ohtani et al shows a method of patterning an amorphous silicon layer and then forming raised source/drains in this layer by plasma doping. U.S. Pat. No. 4,912,065 to Mizuno et al teaches a plasma doping process. U.S. Pat. No. 5,718,800 to Juengling and 6,136,643 to Jeng et al show contact processes and nitride caps over gates.
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method of raised contact formation in the fabrication of integrated circuits.
It is a further object of the invention to form raised contacts using polysilicon.
Another object of the invention is to form raised contacts using polysilicon deposited by a hemispherical grain (HSG) method.
Yet another object of the invention is to form raised polysilicon contacts integrated with a low energy implantation method to form shallow junctions.
A still further object of the invention is to form raised polysilicon contacts using selective polysilicon deposition at a controlled grain size wherein the polysilicon layer is implanted to achieve ultra shallow junction devices.
In accordance with the objects of the invention, an integrated raised contact formation method to achieve ultra shallow junction devices is achieved. Semiconductor device structures are provided in and on a substrate and covered with a dielectric layer. The dielectric layer is etched through to form first openings to the substrate. The surface of the substrate exposed within the first openings is amorphized. A silicon layer is selectively formed on the amorphized substrate surface. Then, ions are implanted into the silicon layer to provide dopants into the raised contacts. Thereafter, the dielectric layer is etched through to form second openings to gates. The first and second openings are filled with a conducting layer to complete formation of contacts in the fabrication of an integrated circuit device.